In a CCD sensor for electronic imaging applications, the horizontal frame rate is determined by a waveform commonly known as the pixel clock. The pixel clock is typically a train of pulses having a substantially 50 percent duty cycle at a constant repetition rate known as the pixel frequency. To extract a video signal from the CCD sensor, three trains of additional control pulses are needed, all having specific timing relationships with respect to the pixel clock. Each pulse of the first train, called a reset pulse, biases an output FET (field effect transistor) amplifier of the CCD sensor to a precharge level. The pixel clock moves the charge representing information out of the CCD sensor. A correlated double sample and hold circuit is normally provided in association with the CCD sensor to extract the value of the video signal. The correlated double sample and hold circuit needs two precisely positioned pulses to operate, namely, a clamp pulse and a sample pulse. The clamp pulses form the second of the three trains of additional control pulses and the sample pulses the third. For the CCD sensor to operate properly, the leading edges of the reset, clamp, and sample pulses need to be precisely positioned with respect to the leading edges of the corresponding pixel clock pulses as respectively different proportions of the period of the pixel clock. If the pixel frequency (and, hence, the horizontal frame rate of the CCD sensor) is changed, it is important that the relative timing relationships between the reset, clamp, and sample pulses and the pixel clock, as respectively different proportions of the pixel clock period, track one another by remaining the same.
In the past, the general practice in the art has been to delay the leading edges of the reset, clamp, and sample pulses with respect to the leading edges of the corresponding pixel clock pulses with fixed time delay circuits. Such circuits, which may be either digital or analog, are commonly known as skewing circuits. Although skewing circuits are satisfactory as long as the pixel frequency remains constant, problems arise if the pixel frequency is changed. Because the time delay introduced by each skewing circuit is not frequency dependent, the delay becomes a larger proportion of the pixel clock period if the pixel frequency is increased (decreasing the pixel clock period) or a smaller proportion of the pixel clock period if the pixel frequency is decreased (increasing the pixel clock period). To avoid undesirable changes in the proportions of the pixel clock period constituting the delays for the respective control pulses, it has been necessary to change skewing circuits whenever the pixel frequency is changed. Changing skewing circuits has been an undesirable complication and expense.